1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device, and more particularly to an EEPROM having control gate electrode and source region patterns formed in parallel with each other and erasing gate electrode patterns formed to intersect the control gate electrode and source region patterns and a method for manufacturing the same.
2. Description of the Related Art
An EEPROM is widely known as an electrically erasable and programmable nonvolatile semiconductor memory device. The EEPROM is generally constructed by a memory cell transistor having a three-layered gate structure including a floating gate electrode formed of a first polysilicon layer, an erasing gate electrode formed of a second polysilicon layer and a control gate electrode formed of a third polysilicon layer. In this type of memory device, the control gate electrode and source region patterns are alternately arranged in parallel with each other and the erasing gate electrode patterns are formed to extend in the channel length direction of the memory cell transistor or in a direction intersecting the control gate electrode and source region patterns in order to reduce the size of the memory cell transistor. The construction of the above EEPROM is described in U.S. Pat. No. 4,466,081, for example.
In the above EEPROM, the control gate electrode and the source region inevitably intersect the erasing gate electrode. In this case, a problem occurs in that part of the source region which intersects the erasing gate electrode. When memory data in a memory cell is erased, a voltage applied to the erasing gate electrode is raised so as to drive out electrons stored in the floating gate electrode to the erasing gate electrode by making use of the tunnel effect of a thin oxide film disposed between the floating gate electrode and the erasing gate electrode. For this reason, in the erasing operation, a high voltage is applied to the erasing gate electrode. The source region which intersects the erasing gate electrode is always set at a ground potential, or it is always applied with 0 V, for example. Therefore, if a voltage of 20 V is applied to the erasing gate electrode, for example, a voltage of as high as 20 V is applied between the erasing gate electrode and the source region at the intersecting portion thereof. In this case, if the oxide film disposed between the erasing gate electrode and the source region is thin (for example, with a thickness of approximately 300 .ANG.), an electric field of as strong as approximately 6.7 MV/cm is applied to the oxide film. As a result, the oxide film may be easily broken down, degrading the reliability of the memory device.
In order to solve the problem caused by the high potential difference occurring in the above intersecting portion in the erasing operation, the oxide film disposed between the erasing gate electrode and the source region at the intersection portion thereof is generally made thick. When the thickness of the oxide film disposed between the erasing gate electrode and the source region is set to approximately 2000 .ANG., the electric field applied to the oxide film is reduced to approximately 1 MV/cm, preventing the oxide film from dielectric breakdown.
However, problems occur when a thick oxide film is selectively formed in each intersecting portion. In order to form the thick oxide film only in the intersecting portion, a thick oxide film is formed on the entire surface of the structure and then that portion of the thick oxide film which does not lie in the intersecting portion is selectively removed. In a case where the thick oxide film is formed by the CVD method, for example, the oxide film is formed thick on the semiconductor substrate but is formed thin on the field oxide layer since the growth speed of the oxide film is different on the semiconductor substrate and on the field oxide layer. When the thick oxide film which is not uniform in thickness is selectively removed by an etching process so as to be left behind only in the intersecting portion, that portion of the field oxide layer which lies under the thin oxide film is partly etched and the thickness thereof is reduced. If, in this way, the thickness of the field oxide layer acting as an element isolation region is reduced, leak may occur between elements, degrading the reliability of the memory cell. Further, since the field oxide film is originally formed thin in the bird's beak portion thereof, the substrate surface is exposed in the etching process and a concave or hollow-out portion is formed. Since the hollow-out portion is formed in the surface of the substrate, the width of the gate of each memory cell transistor, and also the widths of the gates of the other transistors incorporated in the EEPROM--all these gates to be formed later--increase, making it difficult to impart desired characteristics to these transistors.